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Assembly Programming
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Introduction to Computer Organization and Architecture

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Introduction to Computer Organization and Architecture

The objective of this lab is to practice:

ARM data definition directives

ARM assembly pseudo instructions

If you would like to leave, and at least 30 minutes have passed, raise your hand and wait for the TA. Show the TA what you did. If, and only if, you did a reasonable effort during the lab, the TA will give you the lab mark.

REVIEW

ARM pseudo-instructions

The ARM assembler supports a number of pseudo-instructions that are translated into the appropriate combination of ARM instructions at assembly time. ARM pseudo-instructions include:

LDR ARM pseudo-instruction

The LDR pseudo-instruction loads a register with either:

  • a 32-bit constant value
  • an address Note that, the LDR instruction can also be used as non-pseudo-instruction, e.g., LDR r1,[r2]

Syntax

The syntax of LDRwhen it is used aspseudo-instructionis:

LDR{condition} register,=[expression | label-expression]

where:

conditionis an optional condition code,registeris the register to be loaded,expressionevaluates to a numeric constant:

If the value of expression is within the range of a MOV or MVN instruction, the assembler generates the appropriate MOV or MVN instruction to perform the task.

If the value of the expression is not within the range of a MOV or MVN instruction, the assembler places the constant in a literal pool and generates a program-counter-relative LDR instruction that reads the constant from the literal pool.

The offset from the PC to the constant must be less than 4KB.

label-expressionis a program-counter-relative expression. The assembler places the value of label-expression (i.e., an address) in a literal pool and generates a program-counter-relative LDR instruction that loads the value from the literal pool.The offset from the PC to the value in the literal pool must be less than 4KB.

 

Usage

The LDR pseudo-instruction is used for two main purposes:

to load a literal constant to a register when an immediate value cannot be moved into the register because it is out of range of the MOV and MVN instructions, which must be represented by a value from 0 to 255 and a rotation.

to load a program-counter-relative address into a register.

 

Example

LDR r1,=0xfff ; loads 0xfff into r1

LDR r1,=0xfff ; loads 0xfff into r1

ADR ARM pseudo-instruction

The ADR pseudo-instruction uses to load a lable address into a register.

Syntax

The syntax of ADR is:

ADR{condition} register, lable expression

where:

conditionis an optional condition code,

registeris the register to load,

lable expressionis to evaluate to an address.

The address can be either before or after the address of the instruction

Usage

ADR always assembles to one instruction. The assembler attempts to produce a single ADD or SUB instruction to load the address. The distance between the address in the lable expression and the ADR instruction MUST be represented as a value from 0 to 255 and a rotation

Example

start MOV r0,#10 ADR r4,start ; => SUB r4,pc,#0xc

PROBLEM SET

Before you start practicing this lab, you need to review and fully understand tutorials 6 and 7

(Tutorial_06_ARM_Data_Definition_Directives.pdf and Tutorial_07_ARM_Pseudo Instructions).

  1. Consider the following assembly programs:

AREA More_data_definitions, CODE, READONLY ENTRY

Addresses

1st byte

2nd byte

3rd byte

4th byte

Comments

0x00000000

0xEA

0xFF

0xFF

0xFE

B instruction encoding

0x00000004

 

 

 

 

 

0x00000008

 

 

 

 

 

0x0000000C

 

 

 

 

 

0x00000010

 

 

 

 

 

0x00000014

 

 

 

 

 

0x00000018

 

 

 

 

 

0x0000001C

 

 

 

 

 

0x00000020

 

 

 

 

 

0x00000024

 

 

 

 

 

0x00000028

 

 

 

 

 

0x0000002C

 

 

 

 

 

0x00000030

 

 

 

 

 

0x00000034

 

 

 

 

 

0x00000038

 

 

 

 

 

0x0000003C

 

 

 

 

 

 

 

loop   B   loop

data_1 SPACE 3

data_2 SPACE 3

data_3 SPACE

3

DCD

0x12345678

DCD

+2_1111000011110000

DCD

-2_1111000011110000

DCW

255

DCW

-255

DCB

&0A

DCD

1,2,3,4

DCB

5

DCD

6

END

 

 

 

ALIG

 

ALIGN

The above program consists of one instruction (the machine code of this branch instruction is “0xEAFFFFFE”) and a bunch of data definition directives.

 

Manually calculate the memory map for the entire program, i.e., mention the address location and the content of each memory location of this program. Use this information to fill the table above. Verify your calculations by assembling the above program and compare the generated machine language code with your calculations.

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