What are the Boolean equations for next state and output logic? Draw the truth table for the next state and output logic for this circuit. 1.D.Computer Science

Question 1. (30 POINTS) Given the FSM schematic below, answer the following questions:

A.) (6 POINTS) What are the Boolean equations for next state and output logic?

B.) (4 POINTS) Is this a Moore or Mealy FSM? Why? Please explain.

C.) (10 POINTS) Draw the truth table for the next state and output logic for this circuit. 1.D.) (10 POINTS) Draw the state transition table for this FSM. Please show your work. 

  1. (20 POINTS) A seven-segment decoder is a digital circuit that displays an input value 0 through 9 as a digital output in the 7-segment display. The behavior of this design can be modeled with the schematic diagram below, where DCBA is the 4-bit input (D is the most significant bit and A is the least significant bit) and abcdefg is the 7-segment

2.A.) (5 POINTS) Draw the truth table for this circuit. Please show your work.

 

2.B.) (10 POINTS) Simplify each output using K-map. Please show your work.

 

2.C.) (5 POINTS) Show which output segments will be ON for each input. Assume all numbers will be displayed as right aligned in the 7-segment output.

3.   (15 POINTS) Write a Verilog program that tests whether a 4-bit input variable is a Fibonacci number or not. Please attach your Verilog code to your submission. Also include a screenshot of your Verilog code, as well as your program execution result as an answer to this question. 

  1. (20 POINTS) Given the following verilog code, draw the corresponding state diagram for module mysterious

(input                        reset, clk, TB, TA, output reg [1:0]     LB, LA);

reg [1:0] cstate, nstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10;

parameter S3 = 2'b11; parameter grn = 2'b00; parameter ylw = 2'b01; parameter rd   = 2'b10;

// state register

always @ (posedge clk, posedge reset) begin

if (reset) cstate <= S0; else cstate <= nstate;

end

// next state logic always @ (*) begin

case (cstate) S0: if (~TA)

nstate = S1; else nstate = S0;

S1: nstate = S2;

S2: if (~TB)

nstate = S3; else nstate = S2;  S3:               nstate = S0; default: nstate = S0;

endcase end

 

// output logic always @ (*) begin

if (cstate == S0) begin LB = rd;

LA = grn; end

else if (cstate == S1) begin LB = rd;

LA = ylw; end

else if (cstate == S2) begin LB = grn;

LA = rd; end

else begin

LB = ylw;

LA = rd;

end end

end module

 

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