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Processor P3 Simulator Manual document describes the operation of the simulator to the processor P3. This allows the program to simulate the functional level of the processor described

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Processor P3 Simulator Manual

1         Introduction

This document describes the operation of the simulator to the processor P3. This allows the program to simulate the functional level of the processor described in Chapters 11 and 12 of the book:

Introduction to Digital Systems and Microprocessors G. Rice,

  1. Miller and A. Oliveira

IST Press, 1st Edition, 2005

P3 simulator consists of two programs, the simulator itself, p3sim, and an assembler, p3as. The program converts p3as described in assembly language programs that processor to an object file. Once converted format for this purpose, the program may be uploaded to p3sim simulator. The simulator p3sim allows not only the normal running and step-by-step program, but also the execution of only one clock cycle. This operating mode is useful for observing the progress step-by- step micro-code. In order to make it more interesting interaction with the microprocessor, they defined a set of input and output devices. In particular, this simulator emulates all the inputs and outputs of DIO5 plate Digilent, Inc.

This document is divided into three parts. The first part introduces the architecture of the processor P3. The second part describes the use of the assembler p3as. The third part presents the p3sim simulator.

2 Architecture Processor P3

2.1 records

The processor P3 contains the following records visible to the programmer;

R0-R7: general purpose registers. The register R0 can not be changed and always has the value

0.

PC: program counter, contains the next instruction address to be executed. It can be accessed directly with assembly instructions only being changed with the execution sequence control instructions.

SP: stack pointer, pointing to the top of the stack. It is also used in an indirect way and can only be manipulated directly (for initialization) through a SP MOV instruction, R [1-7].

RE: status register, register in which is stored the status bits (flags) of the processor described in the following section. Also there are no instructions to manipulate this register directly.

All these registers are initialized to 0 after a reset of the processor.

2.2  Bits of State

From the programmer's perspective, there are five status bits or flags in this processor. The status bits are stored in the 5 least significant bits of the SR register, containing the remaining bits of this register 0.

The meaning of the status bits from the lowest bit to the highest register RE weight, is:

O: overflow or over, indicates that the result of the last arithmetic operation exceeds the capacity of the destination operand. In other words, the result can not be represented in 2's complement with the number of bits available in the destination operand, getting this, so with an incorrect value.

N: negative or sign indicates that the result of the last operation was negative, which in addition to 2 is equivalent to saying that the most significant bit of the destination operand was the first.

C: carry or transport, it indicates that the last operation generated a transport bit beyond the last position in the destination operand. It can also be modified by software through the instructions STC, CLC and CMC.

Z: zero indicates that the result of the last operation was 0. E: enable interrupts, enables or disables interrupts, as is 1 or

  1. This is the only status bit that is only changed by software, through ENI and DSI instructions.

2.3  Memory

The addressable memory space is 64k words (16-bit address bus), where each word is 16 bits (data bus width). Access to a memory location can be done with any instruction, using the appropriate addressing mode.

 

2.4  enistered / Outs

The space of inputs and outputs (I / O) memory is mapped. Memory addresses from FF00h are reserved for the space of inputs / outputs. Thus, an instruction can have access to any input / output device that is mapped to this top area of the processor memory.

In the case of this simulator, input / output devices are available:

  • text window device that provides an interface with the keyboard and the computer monitor. Interface has 4 ports:

    • reading, FFFFh address: port for receiving keyboard characters in the text window;

    • writing, FFFEh address: port that allows you to write a certain character in the text window;

    • state, FFFDh address: port that allows you to test whether there was any button pressed in the text window;

  • control FFFCh address: port that lets you position the cursor in the text window, a position where the next character will be

  • pushbuttons: a set of pressure switches The activation of each of these buttons generates an interrupt vector corresponding to the interrupt.

  • switches, FFF9h address: 8 set of switches whose state can be obtained by reading this address.

  • LEDs, FFF8h address: each word bit written in this port defines which of the 16 LEDs are connected.

 

  • display 7 segments, FFF0 addresses FFF1h, and FFF2h FFF3h: each of these ports writing 7 controls a set of LEDs forming a

  • display LCD or liquid crystal: text display with 16 columns and two It has two write ports:

    • FFF5h address: port that allows you to write a given character on the display;

    • FFF4h address: port that lets you position the cursor on the display, a position where the next character will be

  • mask breaks FFFAh address: Position a filter that allows you to individually select which of the first 16 interrupt vectors (0-15) are enabled. After a reset, all the bits of the interrupt mask are 0.

  • timer device which provides the generation of an interrupt after an actual time interval specified by the user. It has two interface ports:

    • control FFF7h address: port which allows to start (placing the least significant bit to 1) or stop (setting this bit to 0) the

    • count value, FFF6h address: port that allows you to specify the number of intervals of 100 ms after which the timer generates an

Control of these devices is explained in greater detail in Section 4.6.

2.5  interruptions

The simulator provides 15 buttons for generating external interrupts (in addition to these, the simulator is just one source of interrupts, timer). Any of these interruptions leads to the activation of a signal INT on one of the external pins of the processor. At the end of execution of each instruction, this signal is tested to see if there are any pending interrupt. In this case, they are carried out two tests:

  • And the status bit (enable interrupts) must be

  • bit of the corresponding interrupt mask this interrupt vector must be

If these two conditions are met, it is called the service routine of this interruption, determined by the interrupt vector read from the data bus. The addresses of the interrupt routines are in the Interrupt vectors table, a table with 256 positions stored in memory from the FE00h address. Thus, the program counter PC is loaded with the value of memory location M [Photo FE00h +].

By default, the interrupt vector associated with each of the 15 interrupt button is simply the button index. However, this can be changed by the user through the simulator interface. This interface also allows you to individually disable each interrupt buttons.

The interrupt vector is associated with the timer 15, and this is fixed.

The call to the interrupt service routine saves the RE register on the stack and disable interrupts (E = 0). It is the programmer's responsibility to safeguard any record that is modified in this routine. The routine must be terminated with the RTI instruction that resets the value of RE from the stack.

3 assembler

3.1         evocation

The assembler p3as recall mode is simply:

p3as $ <name> .as

The assembly file name must have extension .as. If no assembly errors are generated two files:

<Name> .exe                  : File with binary code, ready to run in p3sim simulator.

<Name> .lis   : File with the value assigned to the references used in the assembly program.

3.2 Instruction Set

The assembly instructions accepted by the assembler p3as are presented in Table 11.4 of the book. In addition to these instructions, the assembler recognizes a set of commands (called pseudo- instructions Table 11:16 the book) that, while not generate binary code, allow you to reserve space for variables or make the code more readable. The total instruction recognized by p3as are shown in Table 1, grouped into classes.

The condition .cond in conditional jump instructions (... BR cond, cond JMP and CALL cond) can be one of:

O, NO excess status bit (overflow) N, NN: signal status bit (negative) C, NC: transport status bit (carry)

Z, NZ: zero state bit are met (enable)

Pseudo

arithmetical

logical

displacement

Control

Transfer.

generic

ORIG

BUSINESS

WITH

SHR

BR

MOV

NOP

EQU

INC

AND

SHL

BR. cond

MVBH

ENI

WORD

DEC

OR

SHRA

JMP

MVBL

DSI

STR

ADD

XOR

sHLA

JMP.

cond

XCH

STC

TAB

ADDC

TEST

ROR

CALL

PUSH

CLC

 

 

I NI: bit indicating whether there is a pending interrupt P, NP: positive (

 

 

 

 

SUB

 

ROL

CALL.

cond

POP

CMC

Subb

RORC

RET

CMP

ROLC

RETN

MUL

 

RTI

DIV

 

INT

Table 1: P3 instruction set.

 

These combinations allow each of these test conditions and make the jump if the condition is 1 or 0, respectively.

Arithmetic instructions assume the operands in addition format for 2. Exceptions to this rule are the multiplication and division to assume unsigned numbers. In the case of these two operations will have to be the programmer to take care of manipulating the signal apart.

In this embodiment, there are directions of 0, 1 and 2 operands. In the second operand instructions, one of which has to be necessarily a record. The other operand may have several addressing modes, as explained below. The details of the operation of each instruction (the operation performed and the bit changed state) are also presented below.

 

3.3            Constants

The fact that the processor P3 to be a 16-bit processor defines the maximum possible to specify a constant. Thus, the valid range for positive integers will be

0-216 - 1 and integers in 2's complement of -215 to +215 - 1.

Constant values can be specified in three ways in assembly code:

numerical value in binary: a numerical constant to be interpreted in binary must be terminated with the letter b; Valid values are between -100000000000000b and

1111111111111111b .

numerical value in octal: to a numerical constant is interpreted to be octal terminated by the letter; Valid values are between -100000o and 177,777th.

numerical value in decimal: any integer value between -32768 and 65535. It may optionally be terminated with the letter D, although this is assumed when no other base is indicated;

numerical value in hexadecimal: a numerical constant to be interpreted in hexadecimal must be terminated with the letter h; Valid values are between -8000h and FFFFh.

Character alphanumeric: a character in single quotes, for example, 'g' is converted to its ASCII code. Note, however, that the use of constants in the middle of assembly code (or any other programming language) is extremely unwise. Instead, you must use the EQU command to define constants (see Section 3.7). This practice on the one hand, makes the code more readable, as the symbol associated with the constant, if suitably chosen, gives a clue about the action that you take, and on the other hand, allows for easier updating of the code, as constants that are associated not have to be changed in various places within the code (perhaps failing to some), but simply in line with the EQU command.

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