how to create module descriptions of simple combinatorial logic circuits in VHDL

INSTRUCTIONS TO CANDIDATES

ANSWER ALL QUESTIONS

In the previous lab session we learned how to create module descriptions of simple combinatorial logic circuits in VHDL, and simulate them to verify the behaviour. In this session we will examine sequential logic, more elaborate test bench techniques, and instantiation of IP blocks (“black boxes”).

 

There are four marked coursework assignments, that can be completed before, during or after the lab session, by the specified deadline. The details of your individual assignments can be found in the on-line DSD2 Coursework System, under the Laboratory 2 tab. The submission of the assignments is done electronically, using the on-line DSD2 Coursework System.

The coursework assignments associated with this lab are marked as follows: Assignment 1 – 1 mark

Assignment 2 – 2 marks

Assignment 3 – 3 marks

Assignment 4 – 4 marks

 

In total, these assignments are worth 10% of your final DSD2 module mark

 

Submission deadlines for each assignment, and maximum marks available in each assignment, are shown on the DSD2 Coursework System webpage.

You are allowed multiple submissions. You may be able to improve your mark in any of the assignments that were awarded less than maximum marks if you submit a revised solution. The maximum mark in any of the assignments is available for the first submission of each assignment. Each subsequent submission has the maximum possible mark reduced by 30% (i.e. it falls-off exponentially: 100%, 70%, 49%, 34.3%, etc. - so that you will always gain some marks if you submit a correct solution). Your final mark for each assignment will be the highest mark achieved in any submission.

 

Please read carefully all instructions before submitting your work. Please note that the marking process is complex, consisting of many individual tests. The marking system gives some feedback, but mistakes in the VHDL code may cause multiple tests to fail, sometimes revealing problems which are caused, but not in a very obvious way, by the actual mistake. Do not rely solely on the feedback given by the system. Double-check everything to make sure you followed the instructions. Debug your code using simulations.

 

The submissions are marked automatically. It is essential that you follow the instructions, you will lose marks if you don't.

 

The penalty for missing the submission deadline is 10% per day.

 

 

Exercise 1. Counter

In this exercise, we will consider a model of a sequential binary counter, and examine some issues related to writing a VHDL test bench that automatically tests a VHDL module. The design files have already been created for you.

 

Download files named counter.vhd and tb_counter.vhd from the Resources section on the DSD2 Coursework System web page.

 

Create a new project on your P: drive. Choose a suitable name and location for the project. Make sure your Project Settings are as shown below:

 

 

From the ISE Project Navigator menu select Project > Add Copy of Source. Locate the previously downloaded files counter.vhd and tb_counter.vhd. Change the file association of ‘tb_counter.vhd’ to ‘Simulation’ (this is a testbench file, changing association ensures that it shows up in the Simulation view, but not in the Implementation view of the design hierarchy list).

 

 

A copy of the files will be made and placed in your new project directory. Note that existing sources can be also added from the menu Project > Add Source (which does not create a copy, but just adds a file existing at some location to the project).

 

The project hierarchy list (in the Simulation view) should now show as follows:

 

Double-click on the tb_counter.vhd and counter.vhd to open them in the text editor. The counter module is a model of an up/down counter with asynchronous preset. Direction of counting is set by signal ‘up’, the counter should increment when up=’1’ and decrement when up=’0’. Examine the VHDL code of the counter and the testbench, and make sure you understand it. The testbench module contains three processes. The first one generates a clock signal, the second one generates other stimuli (preset, and up signals). The third is an output monitoring process.

 

Simulate the testbench. Ensure the simulation runs long enough for you to view the complete waveform. You can set the simulation run time in the properties of the ‘Simulate Behavioural Model’ process, you can also change it in the ISim window that appears after a simulation is launched. Click on the “Run”    button to run for a specified length of time, or you can simply use the “Run All”   button on the toolbar, which will run the entire simulation – but beware, if the testbench contains looping processes and no explicit termination statements it will not end unless it is manually stopped!)

 

When simulating, it is often useful to represent binary data (bit vectors) in a more convenient format. In this case, you should tell the simulator to represent the “count[7:0]” vector as a number. To do this, right-click on “count[7:0]” in the signals list, then select “Radix” and then “Unsigned Decimal”.

 

 

Attachments:

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