A 2-bit ripple-carry adder adds bits (An+1, An) to bits (Bn+1, Bn) and takes into consideration the carry from the previous stage, called Cn-1 where n+1, n and n-1 are indices.
A number of 2-bit ripple-carry adders are used to form a larger M bit ripple-carry adder. For instance, you might be designing a 32-bit ripple-carry adder which performs A + B, where both A and B are 32 bit numbers with
A= A31 A30 … A0
B= B31 B30 … B0
In this case M = 32 and you would use 16 of your 2-bit full-adders to generate the sum
S = S31 S30 … S0
And the Carry out of the full 32 bit ripple-adder is C31
Now your generic 2-bit full adder stage has inputs:
X1, Bit N+1 of number A
Y1, Bit N+1 of number B
X0, Bit N of number A
Y0, Bit N of number B
C-1 Carry bit from the previous stage
It will also have 3 outputs. They are the 2 sum bits and a carry
S0 Representing the sum of X0 and Y0 and C-1 (the carry from any previous stage connected to this stage)
S1 Representing the sum of X1 and Y1 and C0 (the carry from X0 + Y0)
C1 Representing the carry out of your 2-bit full adder
Implementation # 1 (25 pts)
You are given two decoders. 1 of type 3-to-8 decoder and 1 of type 4-to-16 decoder. Use them to implement the outputs of your 2-bit full adder. This means that you need to design circuitry to compute S1, S0 and C1.
In this implementation, you can go ahead and also implement C0 (the carry out of your 0th stage) if you feel you can use C0 in your design to compute some of the other outputs. C0 would have to use one of the two decoders you were given.
Implementation #2 (25 pts)
After your first design, your boss decided to have you make a faster version that would not have the drawback of the delay due to the ripples associated with the calculation of the intermediate carry of your 2-bit adder.
To help, your boss suggests (which means demands) that you design your circuit using a programmable logic array having 5 dedicated input pins and 3 dedicated output pins. There are NO feedback pins.
So, you must design a 2-bit adder (no ripple within a 2 stage) using a programmable logic array having 5 dedicated inputs called A0 A1 B0 B1 C0 in that order from the top line of your PLA where A0 is the least significant bit (LSB and topmost input) and C0 the most significant bit (MSB and bottommost input). There are 3 dedicated outputs and should be named S0, S1 and C1 and be shown in that order from top output to bottom output of your PLA.
To show that you know what you are doing, you will need to label each AND gate in your AND array with the minterm number it recognizes (this can be written in decimal or in binary using C0 as MSB and A0 as LSB). That requirement might make you appreciate the requirement that the inputs be ordered A0 A1 B0 B1 C0. You might notice a relationship between the minterm number and the sum (A1 A0) + (B1 B0) + C0
Implementation #3 (25 pts)
You are now asked to design a 1-bit full adder using a sequential circuit. You are simply asked to provide a state table and a state diagram representing the operation of your 1-bit adder. A 1-bit adder is just one half of your 2-bit ripple adder.
Your 1-bit adder simply adds bits Cin, A and B. Your implementation of your state machine will have a 1 bit input called X that will be used to feed the inputs in that same order: First Cin, then bit A then bit B. To make the notation simpler, just call the inputs C, A and B for Carry, Bit A and Bit B respectively.
A more experienced team member as been assigned to you as a mentor and she is offering the following advices:
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