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Fundamentals Of Computer Systems, Fall 2021 Problem Set #4 Your machine needs to work only in the steady state (i.e., the output is a β€œdon’t care” for the first two cycles).

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Hi. Attaching file for hw that i need help with for fundamentals of computer systems. please refer to harris book in pdf

 

Fundamentals Of Computer Systems, Fall 2021

Problem Set #4

Please write neatly and enter your solutions in the space provided. If you need additional space, please

insert an additional page into the PDF immediately after the problem in question.

For full credit, you must show your work and design process where applicable, so we can see how you

arrived at a solution.

For the design problems in this set, you may use any standard module or logic gates you wish unless

otherwise specified.

As always, all written work is expected to be individual. If you discussed these problems with anyone,

please list them here (excluding teaching staff):

__________________________________

__________________________________

__________________________________

__________________________________

1

Fundamentals Of Computer Systems, Fall 2021

Problem Set #4

1. Re-implement the vending machine controller from lecture, but extended to give change by

releasing nickels. The inputs are the same:

β—‹ 𝑁, 𝐷: single bit inputs indicating whether a nickel or a dime (but never both) have been

inserted

β—‹ 𝐢𝐿𝐾, 𝑅𝑆𝑇: the usual clock and active low reset inputs

The outputs are

β—‹ π‘œπ‘π‘’π‘›: set to 1 for one cycle to vend an item

β—‹ π‘Ÿπ‘’π‘‘π‘’π‘Ÿπ‘›: set to 1 for one cycle to return a nickel

As before, the machine accepts only nickels and dimes, and vends a single item whose price is

15¢. This new machine should accept and credit all coins entered, including while vending or

returning change.

a) Draw a state transition diagram for a Moore implementation of this machine. Your design should

minimize the number of states.

2

Fundamentals Of Computer Systems, Fall 2021

Problem Set #4

b) Using the minimum necessary D flip-flops, set the state encoding and derive expressions for the

next state and output logic.

3

Fundamentals Of Computer Systems, Fall 2021

Problem Set #4

2. Now design a Mealy implementation of the vending machine controller specified in Problem 1.

a) Draw a state transition diagram for the Mealy implementation, again minimizing the number of

states.

4

Fundamentals Of Computer Systems, Fall 2021

Problem Set #4

b) Using the minimum necessary D flip-flops, set a state encoding and derive expressions for the

next state and output logic of the Mealy implementation.

5

Fundamentals Of Computer Systems, Fall 2021

Problem Set #4

3. Consider the finite state machine shown below, whose input is x and output is even.

a) Complete the timing diagram, assuming zero gate delay in any logic and rising-edge

triggered flip-flops.

b) Assume the machine isto be implemented using flip-flops whose setup time is 0.5ns and

propagation delay from clock to Q is 0.5ns. Assuming there is no clock skew, what is the

range of safe critical paths for the next state logic, such that the machine will work at

clock frequencies up to 300MHz?

6

Fundamentals Of Computer Systems, Fall 2021

Problem Set #4

4. In this problem you will design a machine whose single output bit y mirrors the single bit of input

x. The only change in y relative to x is that y is delayed one cycle relative to x, and that single

cycle pulses on x (i.e., x=1 for one cycle in between cycles where x=0) are suppressed (i.e., y=0

the cycle after a single cycle pulse of x=1). For example:

011001011011101011...

011000011011100011...

Your machine needs to work only in the steady state (i.e., the output is a “don’t care” for the first

two cycles).

a) Draw a Mealy state transition diagram for the finite state machine above, minimizing the

number of states.

7

Fundamentals Of Computer Systems, Fall 2021

Problem Set #4

b) Implement your machine using the minimal number of J-K flip-flops and the minimum

number of gates in the next state and output logic. The behavior of a J-K flip-flop is

J K 𝑄𝑛𝑒π‘₯𝑑

0 0 π‘„π‘π‘’π‘Ÿπ‘Ÿ

hold

0 1 0 reset

1 0 1 set

1 1 π‘„π‘π‘’π‘Ÿπ‘Ÿ

toggle

8

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