logo Use CA10RAM to get 10%* Discount.
Order Nowlogo

Consider the MIPS instruction sequence given below. Describe in detail a hardware solution to resolve or mitigate (minimize the effect of) potential hazards.

INSTRUCTIONS TO CANDIDATES
ANSWER ALL QUESTIONS

 It in computer architecture/Assembly language.

 

- Please submit your work in Canvas or as a text/MS-word/PDF attachment by the due time.  Please use only zip for compression. It must be typed, not a scan of handwriting. 

- Please write your name in the assignment header and as a part of the file name of the attachment. 

- It must be your own work – a penalty of at least one grade in your final grade and a report to the Dean of Students will result from sharing work or using other people work.

- Please submit your assignment by the deadline. Late submission will not be accepted. You will get 0 if you miss by 1 minute so please assume a deadline of 11:50 pm.

- Do not submit your assignment via email. 

- Please show all the details of your answers. A correct answer without solution details would receive a grade of 0.

 

1) (20%) Consider the MIPS instruction sequence given below. Describe in detail a hardware solution to resolve or mitigate (minimize the effect of) potential hazards.

addi $5, $3,

beq $5, $3, out  // out is somewhere

 

2) Consider the following CPU / cache / memory specifications and trace:

The cache is an LRU, fully associative, D-cache with 4 lines and 16 bytes per block.

Initially all the valid and dirty bits are 0; All the references are “write” references

References trace: AF, B4, AC, C7, D2, F4, F7, 29, 29, 10, D1

 

a. (15%) Provide the result of the traced memory accesses.  The expected result is H, M, or CM, the location of the actual byte that is written in the block, as well as, a snapshot of the entire cache, including overhead bits, before and after a reference word is issued.

 

b. (15%) Repeat part (a) with the following modified assumption: The cache is an LFU, fully associative, I-cache with 4 lines and 16 bytes per block.

 

c. (15%) Repeat part (a) with the following modified assumption: The cache is an OPT, fully associative, I-cache with 4 lines and 16 bytes per block.

 

3) (15%) For a memory/cache configuration with 64K bytes in the memory, a 4-way (four sets) set associative cache with 4 lines per set and 256 bytes per block, find the number of all of the memory blocks from the entire memory that are mapped to cache set 0. 

 

4) Consider a CPU / cache / memory system where access to the cache is 5 seconds and access to the main memory is 100 seconds. A program that has two components, a read component (R) that is reading integers from memory and a compute component (C) that performs a computation on the integers. The total execution time per integer is the time that it takes to read one integer (TR) and the time that it takes to complete the computation on that integer (TC). TC is fixed and takes 5 seconds.  

a. (5%) Assuming that the cache has a hit ratio of 80% find the ETA of the system.

b. (15%) Starting with no cache, it is given that each 1K-bytes of cache memory contributes 1% to the cache hit ratio and due to power consumption costs $0.01 per second. On the other hand, completing the execution (read and compute) on each integer produces a revenue of $1. What is the revenue per integer per second and the cost per integer per second with 85K-bytes of cache?

 

Related Questions

. Introgramming & Unix Fall 2018, CRN 44882, Oakland University Homework Assignment 6 - Using Arrays and Functions in C

DescriptionIn this final assignment, the students will demonstrate their ability to apply two ma

. The standard path finding involves finding the (shortest) path from an origin to a destination, typically on a map. This is an

Path finding involves finding a path from A to B. Typically we want the path to have certain properties,such as being the shortest or to avoid going t

. Develop a program to emulate a purchase transaction at a retail store. This program will have two classes, a LineItem class and a Transaction class. The LineItem class will represent an individual

Develop a program to emulate a purchase transaction at a retail store. Thisprogram will have two classes, a LineItem class and a Transaction class. Th

. SeaPort Project series For this set of projects for the course, we wish to simulate some of the aspects of a number of Sea Ports. Here are the classes and their instance variables we wish to define:

1 Project 1 Introduction - the SeaPort Project series For this set of projects for the course, we wish to simulate some of the aspects of a number of

. Project 2 Introduction - the SeaPort Project series For this set of projects for the course, we wish to simulate some of the aspects of a number of Sea Ports. Here are the classes and their instance variables we wish to define:

1 Project 2 Introduction - the SeaPort Project series For this set of projects for the course, we wish to simulate some of the aspects of a number of

Ask This Question To Be Solved By Our ExpertsGet A+ Grade Solution Guaranteed

expert
Um e HaniScience

980 Answers

Hire Me
expert
Muhammad Ali HaiderFinance

540 Answers

Hire Me
expert
Husnain SaeedComputer science

978 Answers

Hire Me
expert
Atharva PatilComputer science

599 Answers

Hire Me

Get Free Quote!

357 Experts Online