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Assume an OS uses a 3-level page table; the page size of the system is 256 bytes with a 16-bit virtual address space.

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 Assume an OS uses a 3-level page table; the page size of the system is 256 bytes with a 16-bit virtual address space; the ASID of the current process is 216. At a certain time, the system is having the following TLB states:

ASID VPN PFN   Valid Prot

216        0xBB 0x91 1 ???

112        0x05 0x91 1 ???

216        0xFF 0x23 1 ???

216        0x05 0x12 0 ???

Consider each instruction independently (e.g., for Question “b”, don’t worry how Question “a” changes the TLB). The “Prot” field in a TLB entry is marked as “???”, so no need to worry about that either. 

How many physical memory accesses are needed for each instruction (note not only the operand in instruction but the instruction itself needs to be fetched from physical memory as well)?

And briefly explain why.

(a) 0xAA10: movl  0x1111,  %edi

(b) 0xBB13: addl  $0x3,  %edi

(c) 0x0519: movl  %edi,  0xFF10

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